The invention relates to solid state memory devices for storing digital data; and particularly to a class of such devices commonly referred to as flash memories.
A flash memory is a non-volatile storage device which is based on erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) technologies. As such, these devices can be programmed in the equipment in which they are used by applying a programming-erasing voltage and executing an erasure procedure to set all of the bits in the device to a high logic level. Thereafter, another procedure is used to program the device with new data. It is predicted that flash-type devices will be used in many applications that today are implemented by EPROM, EEPROM, battery-backed static RAM and disk memory.
Standard memories are commonly configured as interleaved banks of devices to obtain improved performance and faster access time. In this technique, two or more banks of identical memory devices are arranged in such a way that the requests for data from each one overlap, i.e. when one bank is delivering data, the other bank is preparing to deliver the next sequential item of data. In this way, slower, cheaper memory devices may be employed which none the less deliver high performance.
One drawback to flash-type memories is that presently available devices must be erased entirely before they can be reprogrammed. If such devices are to be reprogrammed in the equipment, as opposed to being removed for reprogramming, the reprogramming software routines must be stored elsewhere in the equipment. Typically, this is accomplished by providing additional memory devices, such as a non-volatile memory or a separate read only memory for the reprogramming routines.
Another class of flash memory devices has been proposed, but as yet is not commercially available, which are commonly referred to as sectored erase flash memories. These flash memories have a group of storage locations which can never be erased in the circuit, in which an initialization routine or the reprogramming routines reside. While this protected sector overcomes the problem associated with present flash memories, presumably new devices will have to be installed if the protected routines have to be changed. Another problem is that the memory is divided into fixed size sectors that may not optimally meet the size requirements of a particular user.
Therefore, it is desirable to provide flash memories which can store initialization and reprogramming routines in a manner which allows not only the remaining sections of the device to be reprogrammed, but when necessary, allows the initialization and reprogramming routines to be changed.
Furthermore, currently available flash memory devices are eight bits wide, requiring that several of them be connected in parallel in order to store sixteen or thirty-two bit wide data words, required by many microprocessors. Such a parallel connection is well known and has been used with a variety of other types of eight-bit wide memory devices. With the previous parallel configurations, it was quite common to erase and reprogram all of the devices in a memory bank in parallel. That is, a given address is applied to all of the parallel connected devices and the corresponding storage location in each one is erased simultaneously. The storage locations are then tested to verify that they have properly erased. Should a storage location in one of the parallel connected memory devices fail to erase, the process is repeated by erasing all of the parallel connected devices once again.
Although this technique is acceptable with other types of memories, one of the drawbacks of flash type memories is a limitation in the number of erasure cycles to which a given storage location may be subjected. Therefore, subjecting all of the devices in a given bank to additional erasure cycles, when only one device has failed to properly erase, subjects the other devices to needless erasure cycles which may cause permanent damage. As a consequence, a common technique used with flash-type memories is to erase each device of the bank independently so as to subject the devices only to the number of erasure cycles actually required for that device. Although this individual erasure process overcomes the problem of subjecting a given device to needless erasure cycles, significantly greater amount of time is required. Therefore, the designer of a circuit which incorporates a flash memory is faced with the trade-off between parallel erasure process which may over erase the devices and an individual erasure process which is time consuming.